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    The Power of Assertions in SystemVerilog by Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny
Publisher: Springer | 2010 | ISBN: 1441965998 | PDF | 544 pages | 14 MB

This book provides a deeper understanding of the meaning of the enhancements contained in the new SystemVerilog 1800-2009 LRM. In particular, it discusses the context of practical deployment in hardware design projects. The material also addresses language implementation alternatives and their impact on simulation performance as well as the ability to debug them in simulation and formal verification environments. The underlying performance issues are illustrated for practical examples drawn from the author's experience.

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